IDF: Many seeds will soon be ready for the market

IDF: Many seeds will soon be ready for the market 

For the fifth anniversary of the public unveiling of the core platform is Intel's chief technology officer Justin Rattner's keynote at the Intel Developer Forum (IDF) and the current many-core in Intel's labs dedicated Parallelisierungsprojekten. Large scale, the super computer clusters for scientific calculations and simulations, is the Large Hadron Collider in Geneva CERN laboratory an impressive example. There are also projects to parallelize individual servers, desktops or radio stations, thereby making them more efficient. 


Justin Rattner demonstrated for the first time a hybrid Cube Memory: 121 GB, or nearly one terabit per second transfers 
Image: Erich was Bonnert >From CERN particle physicists Andrzej Nowak visited, he is working on the optimization of applications of the CERN super-computer grid for Intel Integrated Core Many Archtitektur (MIC). The approximately 40 million particle collisions per second evaluated the LHC accelerator produce within a year data sets of 25 petabytes. With a 32-nuclear cluster Nowak MIC distribution of the code generated by an approximately 40-times better performance. Simulations have been reduced from minutes to seconds. 

Next year there will be the first products with MIC architecture: First, a many-core chip is code-named Knights Corner on the market, said Rattner. Programmed in parallel with Javascript programs are also dramatically speed up web applications. Intel developers have extended the previously mostly used sequential language with features for data-parallelism. The software engine is called parallel JS provided by Intel Labs Open Source. 


Four stacked DRAM chips are placed on a cube with a hybrid memory controller and connected via Through Silicon Via channels.These numerous buses provide a transmission bandwidth of approximately one Tb / s. 
Image: Intel Rattner gave a 3D-flow simulation (N-body) called River Trail within a Firefox browser show: As a single thread, the application can display three frames per second, parallel were on the four cores of a Core i7 45 fps with much denser and to see faster visualization. In the next version will also be controlled via parallel graphics cores JS. Rattner promised benefits for PC games programmer and on-line simulations and web-based image and video processing. The interoperability with HTML5 and WebCL should be ensured in cooperation with open source organizations. 

Mobile operator China Mobile and Intel are experimenting with quad-core Core i7-based computers as a base station for LTE networks to replace such an expensive telecommunications hub.The radio signals are digitized locally and sent over a fiber network for data centers for processing. Vector Engines to behave like digital signal processors. The next year the Chinese launch their first field trial. 


Despite the name, the Cube is three-dimensional memory chip (pictured right, complete with motherboard), no dice, but relatively flat. Intel's development partner, Micron will manufacture the memory from 2013 series. 
 Intel Rattner Force concluded before a three-dimensional, stacked DRAM memory chip, a joint venture with Micron. Approximately seven times more energy efficient than today's DDR3 memory, provides the prototype data rates of up to one terabit per second.In the "Hybrid Memory Cube" DRAM buffer layers were stacked with documents in a manufacturing process for logic devices with each other. The routing of the pins to DRAM, according to Intel, this can be done by the logic data routes more efficient and more energy efficient. Dramatic improvements should be possible with all the cubes in hybrid devices such as ultra compact books, tablets and smartphones.