With the Hybrid Memory Cube (HMC) and Micron will make much more
efficient memory modules. But so far it had proprietary DRAM concepts in
the highly competitive market is always difficult: Against the cheap
mass-produced goods could prevail only a few approaches, so for example,
failed Virtual Channel, Direct Rambus-or quad-band memory. Through the
cooperation with the competitor and market leader Samsung DRAM Micron
wants to improve the success chances of HMC.
The HMC Consortium (HMCC) is to specify an open, standardized HMC
interface. Partner of HMCC-founders are still the first FPGA specialist
Altera and Xilinx and Open-Silicon. Even though Intel has already
demonstrated at IDF one HMC prototype of the 121 gigabytes of data per
second over bore - that is close to the target value of 1 Tbit / s, 128
Gbyte / s. By comparison, current server with two CPU sockets have six
or eight channels of memory for DDR3 SDRAM. Equipped with PC3-10600
DDR3-1333 DIMMs made chips are a total of approximately 64 GB / s to
85 GB / s can be achieved.
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